About Dr. Rajinder Kumar Bhan

Solid State Physics Laboratory
Defence R&D Organization
Lucknow Road, Timarpur,
Delhi-110054, India
Email: bhan_rk2003@yahoo.com, bhan@sspl.drdo.in

Dr R K Bhan, obtained his MSc (Physics) from Kashmir University in 1982 and PhD in Solid State Physics (Microelectronics) from Delhi University in 1994. He worked as JRF at IIT Delhi in CARE department from 1982 to 1984. He joined SSPL in September 1984. Since then he is working there in the field microelectronic devices. Currently, he heads the Infrared and Silicon MEMS division of the laboratory.

He made significant contributions in the field of infrared detector development, Charge Coupled Devices (CCDs), CMOS devices, infrared detectors modelling and their characterizations. He has more than 80 publications in international journals to his credit. He has also published several technical reports on Infrared detector characterizations and MEMS sensors. His current interests include Infrared sensors (cooled and uncooled), MEMS sensors, CMOS technology, cryogenic characterization of semiconductor devices at wafer level.

As a recognition for his services, he was awarded the “National Science Day Award” in 2008, for his work on IR detectors and associated readout devices by the laboratory. He is also been responsible for planning of infrared activities in SSPL. He is the recipient of Group Technology Award – 2008 for his contributions in the field of “IR measurements” and in 2014 for “MEMS technology at SSPL”.

He is a senior member of Materials Research Society of India. He is also listed in “MARQUIS Who is Who”, America and “Dictionary of International Biography”, London.

An improved analytical method for reducing edge built up and estimation of thickness in selective plating using variable perimeter-to-area ratio window test mask

In this paper, we attempt to present a new approach and analytical relation between perimeter-to-area ratio (P/A) and the plated thickness using Variable Area Window (VAW) test mask for improved thickness estimation. Although, the approach is illustrated using selective plating of gold films by varying two dimensional patterned windows on metallised silicon surface as an example, yet the method can be applied to other cases also. The method includes selective electroplating of gold in rectangular and circular windows wherein P/A of patterned shapes (squares, rectangles and circles) has been varied from 0.001 cm-1 to 0.4 cm-1 i.e. a factor of 400, a range normally used for practical modern MEMS devices. Experiments show that in general the thickness increases with increasing P/A because of current crowding. However, in contrast to using current density for control of this current crowding as reported in literature, we report that by careful design of mask pattern and improved material parameters, one can control and even achieve a slope reversal in the plot of thickness vs. P/A. The increase in thickness as measured by slope of linear fit is about 3 µm/(P/A in µm-1) for sharp edges compared to about 0.8 µm/(P/A in µm-1) for curved edges within the experimental errors. The general applicability of these relations to practical cases is confirmed by analysing the previously reported trends of data from the literature on Ni films using similar patterned shapes.